1/6 data briefing september 2003 complete data available on data-on-disc cd-rom or at www.st.com complete data available on data-on-disc cd-rom or at www.st.com . rev. 1.2 upsd3254a, upsd3254bv upsd3253b, upsd3253bv flash programmable system devices with 8032 microcontroller core features summary n the upsd325x devices combine a flash psd architecture with an 8032 microcontroller core. the upsd325x devices of flash psds feature dual banks of flash memory, sram, general purpose i/o and programmable logic, supervi- sory functions and access via usb, i 2 c, adc, ddc and pwm channels, and an on-board 8032 microcontroller core, with two uarts, three 16-bit timer/counters and two external interrupts. as with other flash psd families, the upsd325x devices are also in-system pro- grammable (isp) via a jtag isp interface. n large 32kbyte sram with battery back-up option n dual bank flash memories C 128kbyte or 256kbyte main flash memory C 32kbyte secondary flash memory n content security C block access to flash memory n programmable decode pld for flexible address mapping of all memories within 8032 space. n high-speed clock standard 8032 core (12-cycle) n usb interface (some devices only) n i 2 c interface for peripheral connections n 5 pulse width modulator (pwm) channels n analog-to-digital converter (adc) n standalone display data channel (ddc) n six i/o ports with up to 46 i/o pins n 3000 gate pld with 16 macrocells n supervisor functions with watchdog timer n in-system programming (isp) via jtag n zero-power technology n single supply voltage C 4.5 to 5.5v C 3.0 to 3.6v figure 1. 52-lead, thin, quad, flat package figure 2. 80-lead, thin, quad, flat package tqfp52 (t) tqfp80 (u) obsolete product(s) - obsolete product(s)
upsd3254a, upsd3254bv, upsd3253b, upsd3253bv 2/6 complete data available on data-on-disc cd-rom or at www.st.com complete data available on data-on-disc cd-rom or at www.st.com . summary description n dual bank flash memories C concurrent operation, read from memory while erasing and writing the other. in-appli- cation programming (iap) for remote updates C large 128kbyte or 256kbyte main flash memory for application code, operating sys- tems, or bit maps for graphic user interfaces C large 32kbyte secondary flash memory di- vided in small sectors. eliminate external ee- prom with software eeprom emulation C secondary flash memory is large enough for sophisticated communication protocol (usb) during iap while continuing critical system tasks n large sram with battery back-up option C 32kbyte sram for rtos, high-level lan- guages, communication buffers, and stacks n programmable decode pld for flexible address mapping of all memories C place individual flash and sram sectors on any address boundary C built-in page register breaks restrictive 8032 limit of 64kbyte address space C special register swaps flash memory seg- ments between 8032 program space and data space for efficient in-application pro- gramming n high-speed clock standard 8032 core (12-cycle) C 40mhz operation at 5v, 24mhz at 3.3v C 2 uarts with independent baud rate, three 16-bit timer/counters and two external inter- rupts n usb interface (some devices only) C supports usb 1.1 slow mode (1.5mbit/s) C control endpoint 0 and interrupt endpoints 1 and 2 n i 2 c interface for peripheral connections C capable of master or slave operation n 5 pulse width modulator (pwm) channels C four 8-bit pwm units C one 8-bit pwm unit with programmable peri- od n 4-channel, 8-bit analog-to-digital converter (adc) with analog supply voltage (v ref ) n standalone display data channel (ddc) C for use in monitor, projector, and tv applica- tions C compliant with vesa standards ddc1 and ddc2b C eliminate external ddc prom n six i/o ports with up to 46 i/o pins C multifunction i/o: gpio, ddc, i 2 c, pwm, pld i/o, supervisor, and jtag C eliminates need for external latches and logic n 3000 gate pld with 16 macrocells C create glue logic, state machines, delays, etc. C eliminate external pals, plds, and 74hcxx C simple psdsoft express software...free n supervisor functions C generates reset upon low voltage or watch- dog time-out. eliminate external supervisor device C reset input pin; reset output via pld n in-system programming (isp) via jtag C program entire chip in 10 - 25 seconds with no involvement of 8032 C allows efficient manufacturing, easy product testing, and just-in-time inventory C eliminate sockets and pre-programmed parts C program with flashlink tm cable and any pc n content security C programmable security bit blocks access of device programmers and readers n zero-power technology C memories and pld automatically reach standby current between input changes n packages C 52-pin tqfp C 80-pin tqfp: allows access to 8032 address/ data/control signals for connecting to external peripherals obsolete product(s) - obsolete product(s)
3/6 upsd3254a, upsd3254bv, upsd3253b, upsd3253bv complete data available on data-on-disc cd-rom or at www.st.com complete data available on data-on-disc cd-rom or at www.st.com . table 1. upsd325x devices product matrix figure 3. tqfp52 connections note: 1. pull-up resistor required on pin 5 (2k w for 3v devices, 7.5k w for 5v devices) for all 52-pin devices, with or without usb function. 2. pin 7 is not connected (nc) for device with no usb function. part no. main flash (bit) sec. flash (bit) sram (bit) macro -cells i/o pins pwm ch. timer / ctr uart ch. i 2 c adc ch. ddc usb v cc mhz pins upsd 3254 a-40 2m 256k 256k 16 37 or 46 5 3 2 1 4 yes yes 5v 40 52 or 80 upsd 3254 bv-24 2m 256k 256k 16 46 5 3 2 1 4 yes 3v 24 80 upsd 3253 b-40 1m 256k 256k 16 37 5 3 2 1 4 yes 5v 40 52 upsd 3253 bv-24 1m 256k 256k 16 37 5 3 2 1 4 yes 3v 24 52 39 p1.5 / adc1 38 p1.4 / adc0 37 p1.3 / txd1 36 p1.2 / rxd1 35 p1.1 / t2x 34 p1.0 / t2 33 v cc 32 xtal2 31 xtal1 30 p3.7 / scl2 29 p3.6 / sda2 28 p3.5 / t1 27 p3.4 / t0 pd1 pc7 pc6 pc5 usbC pc4 usb+ v cc gnd pc3 pc2 pc1 pc0 1 2 3 4 5 (1) 6 7 (2) 8 9 10 11 12 13 52 51 50 49 48 47 46 45 44 43 42 41 40 pb0 pb1 pb2 pb3 pb4 pb5 vref gnd reset pb6 pb7 p1.7/adc3 p1.6/adc2 14 15 16 17 18 19 20 21 22 23 24 25 26 p4.7 / pwm4 p4.6 / pwm3 p4.5 / pwm2 p4.4 / pwm1 p4.3 / pwm0 gnd p4.2 / ddc vsync p4.1 / ddc scl p4.0 / ddc sda p3.0 / rxd p3.1 / txd p3.2 / exint0 p3.3 / exint1 ai05790c obsolete product(s) - obsolete product(s)
upsd3254a, upsd3254bv, upsd3253b, upsd3253bv 4/6 complete data available on data-on-disc cd-rom or at www.st.com complete data available on data-on-disc cd-rom or at www.st.com . figure 4. tqfp80 connections note: nc = not connected 1. pull-up resistor required on pin 8 (2k w for 3v devices, 7.5k w for 5v devices) for all 82-pin devices, with or without usb function. 2. pin 10 is not connected (nc) for device with no usb function. 60 p1.5 / adc1 59 p1.4 / adc0 58 p1.3 / txd1 57 p2.3, a11 56 p1.2 / rxd1 55 p2.2, a10 54 p1.1 / t2x 53 p2.1, a9 52 p1.0 / t2 51 p2.0, a8 50 v cc 49 xtal2 48 xtal1 47 p0.7, ad7 46 p3.7 / scl2 45 p0.6, ad6 44 p3.6 / sda2 43 p0.5, ad5 42 p3.5 / t1 41 p0.4, ad4 pd2 p3.3 /exint1 pd1 pd0, ale pc7 pc6 pc5 usb- pc4 usb+ nc v cc gnd pc3 pc2 pc1 nc p4.7 / pwm4 p4.6 / pwm3 pc0 1 2 3 4 5 6 7 8 (1) 9 10 (2) 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 pb0 p3.2 / exint0 pb1 p3.1 / txd pb2 p3.0 / rxd pb3 pb4 pb5 nc vref gnd reset pb6 pb7 rd, cntl1 p1.7 / adc3 psen, cntl2 wr, cntl0 p1.6 / adc2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 pa7 pa6 p4.5 / pwm2 pa5 p4.4 / pwm1 pa4 p4.3 / pwm0 pa3 gnd p4.2 / dcc vsync p4.1 / ddc scl pa2 p4.0 / ddc sda pa1 pa0 ad0, p0.0 ad1, p0.1 ad2, p0.2 ad3, p0.3 p3.4 / t0 ai05791b obsolete product(s) - obsolete product(s)
5/6 upsd3254a, upsd3254bv, upsd3253b, upsd3253bv complete data available on data-on-disc cd-rom or at www.st.com complete data available on data-on-disc cd-rom or at www.st.com . figure 5. psd module block diagram bus interface wr_, rd_, psen_, ale, reset_, a0-a15 d0 C d7 clkin (pd1) clkin clkin pld input bus prog. port port a prog. port port b power mangmt unit 1 or 2 mbit primary flash memory 8 sectors vstdby pa0 C pa7 pb0 C pb7 prog. port port c prog. port port d pc0 C pc7 pd1 C pd2 address/data/control bus port a ,b & c 2 ext cs to port d 20 input macrocells port a ,b & c 73 73 256 kbit secondary non-volatile memory (boot or data) 4 sectors 256 kbit battery backup sram runtime control and i/o registers sram select perip i/o mode selects macrocell feedback or port input csiop flash isp cpld (cpld) 16 output macrocells flash decode pld ( dpld ) pld, configuration & flash memory loader jtag serial channel ( pc2 ) page register embedded algorithm sector selects sector selects global config. & security ai07803 8 bus interface 8032 bus obsolete product(s) - obsolete product(s)
upsd3254a, upsd3254bv, upsd3253b, upsd3253bv 6/6 complete data available on data-on-disc cd-rom or at www.st.com complete data available on data-on-disc cd-rom or at www.st.com . part numbering table 2. ordering information scheme for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: upsd 3 2 5 4 b v C 24 u 6 t device type upsd = microcontroller psd family 3 = 8032 core pld size 2 = 16 macrocells sram size 5 = 256kbit main flash memory size 3 = 1mbit 4 = 2mbit ip mix a = usb, i 2 c, pwm, ddc, adc, (2) uarts supervisor (reset out, reset in, lvd, wd) b = i 2 c, pwm, ddc, adc, (2) uarts supervisor (reset out, reset in, lvd, wd) operating voltage blank = v cc = 4.5 to 5.5v v = v cc = 3.0 to 3.6v speed C24 = 24mhz C40 = 40mhz package t = 52-pin tqfp u = 80-pin tqfp temperature range 1 = 0 to 70c 6 = C40 to 85c shipping optio n tape & reel packing = t obsolete product(s) - obsolete product(s)
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